The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 21, 2005

Filed:

Apr. 15, 2004
Applicants:

Cornelius Christian Russ, Diedorf, DE;

Phillip Czeslaw Jozwiak, Plainsboro, NJ (US);

Markus Paul Josef Mergens, Ravensburg, DE;

John Armer, Middlesex, NJ (US);

Cong-son Trinh, Plainsboro, NJ (US);

Russell Mohn, Plainsboro, NJ (US);

Koen Gerard Maria Verhaege, Gistel, BE;

Inventors:

Cornelius Christian Russ, Diedorf, DE;

Phillip Czeslaw Jozwiak, Plainsboro, NJ (US);

Markus Paul Josef Mergens, Ravensburg, DE;

John Armer, Middlesex, NJ (US);

Cong-Son Trinh, Plainsboro, NJ (US);

Russell Mohn, Plainsboro, NJ (US);

Koen Gerard Maria Verhaege, Gistel, BE;

Assignees:

Sarnoff Corporation, Princeton, NJ (US);

Sarnoff Europe BVBA, Gistel, BE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L023/62 ;
U.S. Cl.
CPC ...
Abstract

A silicon-on-insulator (SOI) electrostatic discharge (ESD) protection device that can protect very sensitive thin gate oxides by limiting the power dissipation during the ESD event, which is best achieved by reducing the voltage drop across the active (protection) device during an ESD event. In one embodiment, the invention provides very low triggering and holding voltages. Furthermore, the SOI protection device of the present invention has low impedance and low power dissipation characteristics that reduce voltage build-up, and accordingly, enable designers to fabricate more area efficient protection device


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