The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 14, 2005
Filed:
Nov. 07, 2000
Applicants:
Ramesh Padmanabhan, Los Altos, CA (US);
Pradeep Sindhu, Los Altos Hills, CA (US);
Eric M. Verwillow, Palo Alto, CA (US);
Inventors:
Ramesh Padmanabhan, Los Altos, CA (US);
Pradeep Sindhu, Los Altos Hills, CA (US);
Eric M. Verwillow, Palo Alto, CA (US);
Assignee:
Juniper Networks, Inc., Sunnyvale, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F001/04 ;
U.S. Cl.
CPC ...
Abstract
A system for reliably receiving data includes a memory, write logic, and read logic. The write logic receives data and an unreliable clock signal and writes the data to the memory using the unreliable clock signal. The read logic generates a gapped clock signal and reads the data from the memory using the gapped clock signal. The read logic generates the gapped clock signal by turning on and off a constant local clock signal.