The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 14, 2005

Filed:

Jul. 31, 2001
Applicants:

Soon-sung Yoo, Kyoungsangbuk-do, KR;

Dong-yeung Kwak, Taegu, KR;

Hu-sung Kim, Seoul, KR;

Yu-ho Jung, Kyoungsangbuk-do, KR;

Yong-wan Kim, Kyoungsangbuk-do, KR;

Duk-jin Park, Taegu, KR;

Woo-chae Lee, Kyoungsangbuk-do, KR;

Inventors:

Soon-Sung Yoo, Kyoungsangbuk-do, KR;

Dong-Yeung Kwak, Taegu, KR;

Hu-Sung Kim, Seoul, KR;

Yu-Ho Jung, Kyoungsangbuk-do, KR;

Yong-Wan Kim, Kyoungsangbuk-do, KR;

Duk-Jin Park, Taegu, KR;

Woo-Chae Lee, Kyoungsangbuk-do, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G02F001/136 ;
U.S. Cl.
CPC ...
Abstract

A liquid crystal display device includes a substrate, a thin film transistor disposed on the substrate, the thin film transistor including a gate electrode, a source electrode and a drain electrode, a gate line arranged in a first direction on the substrate, the gate line connected with the gate electrode of the thin film transistor, a gate insulation layer disposed on the substrate and covering the gate line and the gate electrode of the thin film transistor, an intrinsic semiconductor layer disposed on the gate insulation layer, an extrinsic semiconductor layer disposed on the intrinsic semiconductor layer, a data line arranged in a second direction substantially perpendicular to the first direction disposed on the extrinsic semiconductor layer, the data line connected to the source electrode of the thin film transistor, first and second dummy metal layers formed over the gate line and arranged on opposite sides of the data line, a passivation layer covering the data line, the source electrode, the drain electrode and the first and second dummy metal layers, and a pixel electrode located at a pixel region defined by an intersection of the gate line and the data line, the pixel electrode contacting the drain electrode of the thin film transistor.


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