The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 14, 2005
Filed:
Jun. 29, 2000
Takatoshi Katsura, Hyogo, JP;
Kenji Itoh, Hyogo, JP;
Hiroaki Nagano, Hyogo, JP;
Youji Isota, Hyogo, JP;
Mitsuhiro Shimozawa, Hyogo, JP;
Tadashi Takagi, Hyogo, JP;
Noriharu Suematsu, Hyogo, JP;
Masayoshi Ono, Hyogo, JP;
Kenichi Maeda, Hyogo, JP;
Takatoshi Katsura, Hyogo, JP;
Kenji Itoh, Hyogo, JP;
Hiroaki Nagano, Hyogo, JP;
Youji Isota, Hyogo, JP;
Mitsuhiro Shimozawa, Hyogo, JP;
Tadashi Takagi, Hyogo, JP;
Noriharu Suematsu, Hyogo, JP;
Masayoshi Ono, Hyogo, JP;
Kenichi Maeda, Hyogo, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
In a multi-layer substrate module receiving from an external earth node supply of a reference potential for grounding, a plurality of ground lines are provided respectively corresponding to a plurality of internal circuits. Moreover, a common node for coupling the ground lines is provided in an insulating layer of the multi-layer substrate module. The common node is electrically coupled to the earth node through a ground pin terminal shared by the plurality of internal circuits. Preferably, the common node is provided in the lowest insulating layer of the multi-layer substrate module. Thus, parasitic inductance of the portion through which an earth current flows, that is, the portion common to the plurality of internal circuits, can be suppressed with a small number of ground pin terminals. Accordingly, the inflow phenomenon of the earth current between the plurality of internal circuits is prevented, enabling stable operation.