The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 14, 2005

Filed:

Sep. 09, 2002
Applicants:

Riccardo Depetro, Domodossola, IT;

Anna Ponza, Cornedo Vincentino, IT;

Antonio Gallerano, Milan, IT;

Inventors:

Riccardo Depetro, Domodossola, IT;

Anna Ponza, Cornedo Vincentino, IT;

Antonio Gallerano, Milan, IT;

Assignee:

STMicroelectronics S.r.l., Agrate Brianza, IT;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L023/76 ;
U.S. Cl.
CPC ...
Abstract

An MOS electronic device is formed to reduce drain/gate capacity and to increase cutoff frequency. The device includes a field insulating layer that covers a drain region, delimits an active area with an opening, houses a body region in the active area, and houses a source region in the body region. A portion of the body region between drain and source regions forms a channel region. A polycrystalline silicon structure extends along the edge of the opening, partially on the field insulating and active layers. The polycrystalline silicon structure includes a gate region extending along a first portion of the edge on the channel region and partially surrounding the source region and a non-operative region extending along a second portion of the edge, electrically insulated and at a distance from the gate region.


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