The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6906354 B1

PDF
Full Text
Expired
Date of Patent:
Jun. 14, 2005

Filed:

Jun. 13, 2001
Applicants:

Louis L. Hsu, Fishkill, NY (US);

Rajiv V. Joshi, Yorktown Heights, NY (US);

Fariborz Assaderaghi, San Diego, CA (US);

Inventors:

Louis L. Hsu, Fishkill, NY (US);

Rajiv V. Joshi, Yorktown Heights, NY (US);

Fariborz Assaderaghi, San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L029/32 ; H01L029/423 ;
U.S. Cl.
CPC ...
Abstract

A T-RAM array having a plurality of T-RAM cells is presented where each T-RAM cell has dual devices. Each T-RAM cell is planar and has a buried vertical thyristor and a horizontally stacked pseudo-TFT transfer gate. The buried vertical thyristor is located beneath the horizontally stacked pseudo-TFT transfer gate. A method is also presented for fabricating the T-RAM array having the buried vertical thyristors, the horizontally stacked pseudo-TFT transfer gates and the planar cell structure.


Find Patent Forward Citations

Hsu, Louis. (2005). T-ram cell having a buried vertical thyristor and a pseudo-tft transfer gate and method for fabricating the same (U.S. Patent No. 6906354). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6906354

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