The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 07, 2005
Filed:
Sep. 03, 2002
Dominik J. Schmidt, San Jose, CA (US);
Perry Chun, Milpitas, CA (US);
Richard C. Saito, Sunnyvale, CA (US);
Eugene Y. Chen, San Jose, CA (US);
Dominik J. Schmidt, San Jose, CA (US);
Perry Chun, Milpitas, CA (US);
Richard C. Saito, Sunnyvale, CA (US);
Eugene Y. Chen, San Jose, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
An method of creating a physical layout of an integrated circuit. A schematic file () is mapped directly to a physical layout using the location of elements and routing of interconnections as specified in the schematic file (). The method takes advantage of constraints on the schematic design to provide the layout file () quickly, without complex routing programs. Design rules violations are anticipated and corrected in some cases. In other cases, the design rule violations are annotated, if the designer intentionally placed them in the design.