The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 07, 2005
Filed:
Oct. 04, 2000
James Daniel Merchant, Starkville, MS (US);
Gordon Carskadon, Starkville, MS (US);
Brian P. Evans, Starkville, MS (US);
Jeffery Scott Hunt, Ackerman, MS (US);
Anup Nayak, Fremont, CA (US);
Andrew Wright, Mountain View, CA (US);
James Daniel Merchant, Starkville, MS (US);
Gordon Carskadon, Starkville, MS (US);
Brian P. Evans, Starkville, MS (US);
Jeffery Scott Hunt, Ackerman, MS (US);
Anup Nayak, Fremont, CA (US);
Andrew Wright, Mountain View, CA (US);
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
A method and system for automatically building a bit order data structure of configuration bits for a programmable logic device. One embodiment of the present invention first identifies a plurality of memory cells in a hierarchical schematic representation of the programmable device. Next, this embodiment determines a plurality of addresses corresponding to the plurality of memory cells. This embodiment next determines a plurality of logical names for the plurality of memory cells. Then, based on an order in which the plurality of addresses are to be loaded into the programmable logic device, this embodiment orders the plurality of logical names for the plurality of memory cells. Another embodiment first accesses a database comprising a plurality of logical names corresponding to a plurality of addresses. Then, this embodiment accesses a database specifying an order in which the plurality of addresses are to be loaded into the programmable logic device. Next, this embodiment orders the plurality of logical names based on the order specified in the database from the previous step.