The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 07, 2005
Filed:
Jun. 17, 2003
Saeed Abbasi, Norborth, PA (US);
Martin E. Perrigo, Newtown, PA (US);
Carol A. Price, Jamison, PA (US);
Saeed Abbasi, Norborth, PA (US);
Martin E. Perrigo, Newtown, PA (US);
Carol A. Price, Jamison, PA (US);
ATI Technologies, Inc., Thornhill, CA;
Abstract
A delay locked loop (DLL) circuit having gain control is presented. The DLL circuit includes a bias generator responsive based on an error signal to produce first and second bias voltages to control a plurality of differential delay elements. The bias generator includes a bias current generator having a fixed voltage-controlled current source and a dynamic voltage-controlled current source to generate a bias current, and a bias voltage generator for receiving the bias current and generating first and second bias voltages. The bias generator can generate multiple current levels in different modes of operation. Each of the current levels of the bias generator allows a small range of currents and therefore small values of gain factors (K). Low Kvalues leads to lower jitter and better control over feedback stability, resulting in an increase in the range of operational frequencies.