The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2005

Filed:

Jun. 20, 2002
Applicant:

Richard J. Nathan, Morgan Hill, CA (US);

Inventor:

Richard J. Nathan, Morgan Hill, CA (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L023/488 ; H05K007/02 ;
U.S. Cl.
CPC ...
Abstract

A carrier for an integrated chip is embedded into a substrate, so that stresses due to thermal expansion are uniformly distributed over an interface between the substrate and the carrier (hereinafter 'embedded carrier'). Such an embedded carrier may be formed of a material having a coefficient of thermal expansion similar or identical to the coefficient of thermal expansion of an integrated circuit chip to be mounted thereon, so as to eliminate stresses (due to thermal expansion) at joints between the carrier and the integrated circuit chip. The just-described joints may be formed by any method well known in the art, e.g. flip-chip bonding. Such packaging of one or more integrated circuit chip(s) eliminates reliability issues associated with conventional flip chip bonded components, which are caused by, for example, concentration of stresses in conventional solder ball interconnections between a chip and a substrate.


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