The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 07, 2005
Filed:
Feb. 03, 2003
Kenichi Ookubo, Kanagawa, JP;
Hideki Mori, Kanagawa, JP;
Shigeru Kanematsu, Kanagawa, JP;
Sony Corporation, , JP;
Abstract
A semiconductor device () according to the present invention comprises a vertical PNP bipolar transistor (), an NMOS transistor () and a PMOS transistor () that are of high dielectric strength, and a P-type semiconductor substrate, as shown in FIG.. A substrate isolation layer () of the PNP bipolar transistor (), a drain buried layer () of the NMOS transistor (), and a back gate buried layer () of the PMOS transistor () are formed simultaneously by selectively implanting N-type impurities, such as phosphorous, in the semiconductor substrate (). This invention greatly contributes to curtailing the processes of fabricating BiCMOS ICs and the like including vertical bipolar transistors with easily controllable performance characteristics, such as a current amplification factor, and MOS transistors with high dielectric strength and makes even more miniaturization of such ICs achievable.