The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2005

Filed:

Mar. 28, 2003
Applicants:

Alain Blosse, Belmont, CA (US);

Krishnaswamy Ramkumar, San Jose, CA (US);

Prabhuram Gopalan, Fremont, CA (US);

Inventors:

Alain Blosse, Belmont, CA (US);

Krishnaswamy Ramkumar, San Jose, CA (US);

Prabhuram Gopalan, Fremont, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L021/3205 ;
U.S. Cl.
CPC ...
Abstract

In one embodiment, a gate of a transistor is formed by performing a first thermal treatment on a silicon layer, forming a metal stack over the silicon layer, and performing a second thermal treatment on the metal stack. The first thermal treatment may be a rapid thermal annealing step, while the second thermal treatment may be a rapid thermal nitridation step. The resulting gate exhibits relatively low interface contact resistance between the silicon layer and the metal stack, and may thus be advantageously employed in high-speed devices.


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Blosse, Alain. (2005). Gate electrode for mos transistors (U.S. Patent No. 6902993). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6902993

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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