The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2005

Filed:

Nov. 14, 2002
Applicants:

Pooran Chandra Joshi, Vancouver, WA (US);

John W. Hartzell, Camas, WA (US);

Masahiro Adachi, Vancouver, WA (US);

Yoshi Ono, Camas, WA (US);

Inventors:

Pooran Chandra Joshi, Vancouver, WA (US);

John W. Hartzell, Camas, WA (US);

Masahiro Adachi, Vancouver, WA (US);

Yoshi Ono, Camas, WA (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L021/00 ; H01L021/84 ;
U.S. Cl.
CPC ...
Abstract

An oxide interface and a method for fabricating an oxide interface are provided. The method comprises forming a silicon layer and an oxide layer overlying the silicon layer. The oxide layer is formed at a temperature of less than 400° C. using an inductively coupled plasma source. In some aspects of the method, the oxide layer is more than 20 nanometers (nm) thick and has a refractive index between 1.45 and 1.47. In some aspects of the method, the oxide layer is formed by plasma oxidizing the silicon layer, producing plasma oxide at a rate of up to approximately 4.4 nm per minute (after one minute). In some aspects of the method, a high-density plasma enhanced chemical vapor deposition (HD-PECVD) process is used to form the oxide layer. In some aspects of the method, the silicon and oxide layers are incorporated into a thin film transistor.


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