The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 31, 2005

Filed:

Feb. 04, 1999
Applicants:

Brett Howard, Nepean, CA;

Peter Selwyn, Lanark, CA;

Shawn Lennox, Ottawa, CA;

Clayton Cameron, Carleton Place, CA;

Michel Lamarche, Vanier, CA;

Lorne Flindall, Ottawa, CA;

Andrew Robison, Ottawa, CA;

Wajdi Feghali, Ottawa, CA;

Inventors:

Brett Howard, Nepean, CA;

Peter Selwyn, Lanark, CA;

Shawn Lennox, Ottawa, CA;

Clayton Cameron, Carleton Place, CA;

Michel Lamarche, Vanier, CA;

Lorne Flindall, Ottawa, CA;

Andrew Robison, Ottawa, CA;

Wajdi Feghali, Ottawa, CA;

Assignee:

Alcatel Canada Inc., Kanata, CA;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L009/00 ;
U.S. Cl.
CPC ...
Abstract

A system for ciphering data for transmission by a communication device is provided. The system includes a memory device having a memory buffer a first access port connected to the memory buffer and a second access port connected to the memory buffer. The system also has a data processing processor connected to the first access port via a first bus and a ciphering processor connected to the second access port via a second bus. The first access port and the second access port each provide mutually independent access to the memory buffer. The second bus is not connected to the first bus. The data processing processor is adapted to receive the data and provide the data to the memory buffer over the first bus. The ciphering processor is adapted to retrieve the data from the memory buffer over the second bus, generate ciphered data from the data, generate integrity check information for the ciphered data using the data and provide the ciphered data to the memory buffer over the second bus.


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