The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 31, 2005
Filed:
Feb. 22, 2001
Roy Daron Cideciyan, Rueschlikon, CH;
Jonathan Darrel Coker, Rochester, MN (US);
Ajay Dholakia, Gattikon, CH;
Evangelos S. Eleftheriou, Zurich, CH;
Richard Leo Galbraith, Rochester, MN (US);
Thomas Mittelholzer, Zurich, CH;
David James Stanek, Rochester, MN (US);
Roy Daron Cideciyan, Rueschlikon, CH;
Jonathan Darrel Coker, Rochester, MN (US);
Ajay Dholakia, Gattikon, CH;
Evangelos S. Eleftheriou, Zurich, CH;
Richard Leo Galbraith, Rochester, MN (US);
Thomas Mittelholzer, Zurich, CH;
David James Stanek, Rochester, MN (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method and apparatus are provided for implementing soft-input soft-output iterative detectors/decoders. Soft-input information is added directly to incoming channel samples. Input signals comprising the received incoming channel samples with the added soft-input information are detected using a detector trellis. Branch metric terms are transformed to shift all time varying terms with the added soft-input information and some constant terms after an add compare select (ACS) unit. The shifted time varying terms with the added soft-input information and the shifted constant terms are added directly to state metric terms. The soft-input information is added directly to incoming channel samples and the computation of branch metrics is not affected. This allows optimization of a dual-max detector and soft-input soft-output Viterbi detector architectures to minimize hardware complexity and power consumption.