The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 31, 2005

Filed:

Jun. 26, 2003
Applicants:

Olivier A. Saint-luc, Santa Cruz, CA (US);

Jackie Chu, Fremont, CA (US);

Inventors:

Olivier A. Saint-Luc, Santa Cruz, CA (US);

Jackie Chu, Fremont, CA (US);

Assignee:

Virtual Silicon Technology, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K017/60 ;
U.S. Cl.
CPC ...
Abstract

An input stage circuit for an LVDS circuit. The input stage has a folded cascode that receives input signals. The folded cascode has a first input circuit and a second input circuit. The first input circuit receives a first input signal from a connected circuit and the second input circuit receives a second signal from the connected circuit. A first current mirror receives signals from the first input circuit of said folded cascode. A second current mirror receives signals from the second input circuit. The first current mirror and the second current mirror are connected to a common output to merge signals from the first and second input circuits. A diode adjusts a voltage level of the signals to an output voltage.


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