The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 31, 2005

Filed:

Feb. 27, 2003
Applicants:

Massimo Sutera, Sunnyvale, CA (US);

David A. Bunsey, Jr., Santa Clara, CA (US);

Daniel Y. Cheung, Cupertino, CA (US);

Lan Lee, Palo Alto, CA (US);

Kevin B. Normoyle, Santa Clara, CA (US);

Sung-hun OH, Sunnyvale, CA (US);

Shi-chin Ou-yang, San Francisco, CA (US);

Ivana Capellano, Palermo, IT;

Inventors:

Massimo Sutera, Sunnyvale, CA (US);

David A. Bunsey, Jr., Santa Clara, CA (US);

Daniel Y. Cheung, Cupertino, CA (US);

Lan Lee, Palo Alto, CA (US);

Kevin B. Normoyle, Santa Clara, CA (US);

Sung-Hun Oh, Sunnyvale, CA (US);

Shi-Chin Ou-Yang, San Francisco, CA (US);

Ivana Capellano, Palermo, IT;

Assignee:

Sun Microsystems, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L007/00 ;
U.S. Cl.
CPC ...
Abstract

In an embodiment, present application describes a system and method to detect the alignment of multiple clocks in multi-clock domains system. In some variations, multiple clocks are derived from one or more reference clocks using various PLLs. The derived clocks maintain frequency relationship with the reference clock. In some variations, a relationship between the frequencies of various clocks is used to generate the alignment signals in the domain of one of the clocks.


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