The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 31, 2005

Filed:

Feb. 04, 2001
Applicants:

Tadashi Komiyama, Kofu, JP;

Akitoshi Hara, Fujimi-machi, JP;

Eiichi Sato, Okaya, JP;

Inventors:

Tadashi Komiyama, Kofu, JP;

Akitoshi Hara, Fujimi-machi, JP;

Eiichi Sato, Okaya, JP;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L021/48 ;
U.S. Cl.
CPC ...
Abstract

Certain embodiments of the present invention relate to a method for manufacturing a semiconductor chip, a method for manufacturing a semiconductor device, a semiconductor chip, a semiconductor device, a connection substrate and an electronic apparatus, in which semiconductor chips stacked in layers are electrically connected to one another without using wires. In one embodiment, after an electrodeis formed on a surfaceof a first semiconductor chipa holeis formed from an opposite surfacethereof until a tungsten layerof the electrodeis exposed. A protrusionis formed by etching on a surfaceof a second semiconductor chipand thereafter an abutting electrodeis formed on an apex section of the protrusionThe first semiconductor chipand the second semiconductor chipare stacked on top of the other such that the abutting electrodecontacts the electrodeAs a result, the path between the electrodes becomes shorter and therefore signal delays are inhibited or prevented. Also, there are no restrictions on the area of semiconductor chips to be stacked. As a result, semiconductor chips having the same area can be stacked in layers, and thus the size of the semiconductor devicecan be reduced.


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