The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6900075 B1

PDF
Full Text
Expired
Date of Patent:
May. 31, 2005

Filed:

Oct. 31, 2003
Applicants:

John Jensen, Portland, OR (US);

Robert Muller, Portland, OR (US);

Mark Simmons, Vancouver, WA (US);

Inventors:

John Jensen, Portland, OR (US);

Robert Muller, Portland, OR (US);

Mark Simmons, Vancouver, WA (US);

Assignee:

LSI Logic Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L021/44 ; H01L021/48 ; H01L021/50 ; H01L021/337 ; H01L021/4763 ;
U.S. Cl.
CPC ...
Abstract

An embodiment of the present invention provides a novel method which makes LVR to HVR registration possible by wrapping the X and Y scribes around each instance of each layer on both the LVR and HVR reticles; standard HVR reticles and LVR reticles will not align to one another due to registration and electrical test structures in the scribe being in different locations. Another embodiment of the present invention addresses the loss of die per wafer due to increased sribe area when using LVR and HVR reticles in the same set.


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Jensen, John. (2005). Mixed lvr and hvr reticle set design for the processing of gate arrays, embedded arrays and rapid chip products (U.S. Patent No. 6900075). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6900075

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