The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 24, 2005

Filed:

Nov. 19, 2002
Applicants:

Yoichi Koyanagi, Cupertino, CA (US);

Richard L. Schober, Jr., Cupertino, CA (US);

Raghu Sastry, Santa Clara, CA (US);

Hirotaka Tamura, Atsugi, JP;

Inventors:

Yoichi Koyanagi, Cupertino, CA (US);

Richard L. Schober, Jr., Cupertino, CA (US);

Raghu Sastry, Santa Clara, CA (US);

Hirotaka Tamura, Atsugi, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06K005/04 ;
U.S. Cl.
CPC ...
Abstract

A method and system performs automatic deskew tuning and alignment across high-speed, parallel interconnections in a high performance digital system to compensate for inter-bit skew. Rather than using a VDL, digital elements such as registers and multiplexers are used for performing the automatic deskew tuning and alignment procedure. The result is a simpler, more robust deskew system capable of operating over a wider range of input values with greater accuracy and over a broader range of temperatures. In addition, the method and apparatus performs a one to four unfolding of the signal on each interconnection. The system includes a deskew controller and a plurality of deskew subsystems. The deskew controller automatically computes the amount of delay needed to correct the skew on each interconnection and feeds a different (or appropriate) delay value to each deskew subsystem located at the receiving end of each interconnection.


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