Efficient method for mode change detection and synchronization

Abstract

A processor is configured to operate in a modes which utilize segmentation and which do not utilize segmentation. The processor includes circuitry which is configured to detect and respond to mode and state changes. The circuitry is configured to determine whether a segmentation state of the processor changes in response to execution of a control transfer operation. If the segmentation state does not change as a result of the transfer instruction, execution of instructions may continue sequentially and a corresponding first check performed. However, if the segmentation state does change as a result of the transfer instruction, a flush of the pipeline is initiated prior to performing a corresponding second check. When a first mode of operation is detected a limit check may be performed, while a canonical check may performed when a second mode of operation is detected. A special register is defined which is configured to indicate changes in segmentation state subsequent to a control transfer operations. A read of the special register may then be performed in order to determine whether a state change is indicated.