The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 24, 2005
Filed:
May. 05, 2003
Tan Du, Plano, TX (US);
Tan Du, Plano, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
Disclosed are methods, systems, and algorithms for accurately measuring a DC voltage signal (V) using a sigma-delta modulator (). The preferred embodiments disclose determining a fundamental period (T) of the pattern noise cycle of sigma-delta modulator output at a given DC input (V), and mapping a one-to-one relationship to the ratio of Vto reference voltage (V). Methods, systems, and algorithms according to the invention include the conversion of a DC input (V) into a digital bitstream that periodically provides low-resolution high-frequency digital words (D) representative of the DC input (V). The low-resolution high-frequency words (D) are in turn periodically converted into high-resolution low-frequency words (D) representative of the DC input (V). A fundamental pattern noise frequency (F) of modulator at DC input (V) is determined, and a DC measurement result (D) is output at intervals (1/f) equal to an integer multiple of the fundamental pattern noise cycle (1/F) by taking the sum of the high-resolution low-frequency words (D) at such intervals (1/f). Embodiments of the invention are disclosed in which the measurements results (D) have an error level less than or equal to a selected relative error level (E).