The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 24, 2005
Filed:
Mar. 24, 2003
Jeffery Don Dugger, Atlanta, GA (US);
Tyson S. Hall, Cleveland, TN (US);
Paul Hasler, Atlanta, GA (US);
David V. Anderson, Alpharetta, GA (US);
Paul D. Smith, Marietta, GA (US);
Matthew Raymond Kucic, Austell, GA (US);
Abhishek Bandyopadhyay, Atlanta, GA (US);
Jeffery Don Dugger, Atlanta, GA (US);
Tyson S. Hall, Cleveland, TN (US);
Paul Hasler, Atlanta, GA (US);
David V. Anderson, Alpharetta, GA (US);
Paul D. Smith, Marietta, GA (US);
Matthew Raymond Kucic, Austell, GA (US);
Abhishek Bandyopadhyay, Atlanta, GA (US);
Georgia Tech Research Corp., Atlanta, GA (US);
Abstract
In one exemplary embodiment, a programmable analog array (PAA) contains a configurable analog matrix having two floating-gate field effect transistors (FETs). Also contained in the PAA is an interconnect circuit that is programmable to configure the configurable analog matrix to operate in one or more of several matrix modes. A few examples of such matrix modes include a switching matrix mode, a memory matrix mode, and a computing matrix mode. In an exemplary method of configuring the PAA. PAA, the the method includes programming an interconnection, for example, between a first terminal of the first floating-gate FET and a first terminal of the second floating-gate FET. The method further includes programming an interconnection, for example, between a gate terminal of the first floating-gate FET and a fixed voltage source, for setting a floating gate charge on the first floating-gate FET.