The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 24, 2005
Filed:
Apr. 12, 2004
Cornelius Christian Russ, Princeton, NJ (US);
John Armer, Middlesex, NJ (US);
Markus Paul Josef Mergens, Plainsboro, NJ (US);
Phillip Czeslaw Jozwiak, Plainsboro, NJ (US);
Cornelius Christian Russ, Princeton, NJ (US);
John Armer, Middlesex, NJ (US);
Markus Paul Josef Mergens, Plainsboro, NJ (US);
Phillip Czeslaw Jozwiak, Plainsboro, NJ (US);
Sarnoff Corporation, Princeton, NJ (US);
Abstract
An ESD protection circuit for a semiconductor integrated circuit (IC) having protected circuitry, includes an SCR having at least one finger. Each finger includes a PNP transistor and an NPN transistor, where an emitter of the PNP and NPN transistors is respectively coupled between an I/O pad of the IC and ground, a base of the PNP transistor being coupled to a collector of the NPN transistor, and a base of the NPN transistor being coupled to a collector of the PNP transistor. The NPN transistor of each finger further includes a first gate for triggering said finger. A PMOS transistor includes a source and a drain respectively coupled to the I/O pad of the IC and the first gate of the NPN transistor. Further, a gate of the PMOS transistor is coupled to a supply voltage of the IC.