The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 24, 2005
Filed:
May. 30, 2002
Cong Q. Khieu, San Jose, CA (US);
Chaidir Tjakra, Foster City, CA (US);
Louise Gu, Fremont, CA (US);
Cong Q. Khieu, San Jose, CA (US);
Chaidir Tjakra, Foster City, CA (US);
Louise Gu, Fremont, CA (US);
Sun Microsystems, Inc., Palo Alto, CA (US);
Abstract
Disclosed is a high voltage decoupling capacitor-biasing circuit with no dc current. In one embodiment, the circuit includes a power supply node, a ground node, a common node, a first p-channel FET, a first n-channel FET, and a common node biasing circuit. The first p-channel FET includes a source, gate, and drain, wherein the source and drain of the first p-channel FET are coupled to the power supply node, and wherein the gate of the first p-channel FET is coupled to the common node. The first n-channel FET includes a source, gate, and drain, wherein the source and drain of the first n-channel FET are coupled to the ground node, and wherein the gate of the first n-channel FET is coupled to the common node. The common node biasing circuit is coupled between the power supply and ground nodes. The common node biasing circuit is configured to maintain the common node at a predetermined voltage above ground by charging up or charging down the common node. Further, the common node biasing circuit is configured to transmit only AC current to or from the ground node.