The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 24, 2005
Filed:
May. 13, 2003
Applicants:
Feng Chen, Plano, TX (US);
Donald C. Richardson, Plano, TX (US);
Christopher L. Betty, Arlington, TX (US);
Inventors:
Feng Chen, Plano, TX (US);
Donald C. Richardson, Plano, TX (US);
Christopher L. Betty, Arlington, TX (US);
Assignee:
Texas Instruments Incorporated, Dallas, TX (US);
Primary Examiner:
Int. Cl.
CPC ...
H03L005/00 ;
U.S. Cl.
CPC ...
Abstract
A technique is provided to linearize a MOS switch on-resistance and the nonlinear junction capacitance. The technique linearizes the sampling switch by using a buffer having substantially unity gain with proper DC shift to drive an isolated bulk terminal of the MOS well to improve the spurious free dynamic range (SFDR). In this way, the 2nd-order effect such as nonlinear body effect (V(V)) and nonlinear junction capacitance (C(V)) can be substantially removed.