The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 24, 2005

Filed:

Aug. 19, 2003
Applicants:

In-soo Cho, Kyunggi-do, KR;

Jae-min Yu, Seoul, KR;

Byung-goo Jeon, Yongin-shi, KR;

Jun-yeoul You, Suwon, KR;

Chang-yup Lee, Kyunggi-do, KR;

Inventors:

In-Soo Cho, Kyunggi-do, KR;

Jae-Min Yu, Seoul, KR;

Byung-Goo Jeon, Yongin-shi, KR;

Jun-Yeoul You, Suwon, KR;

Chang-Yup Lee, Kyunggi-do, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L021/336 ;
U.S. Cl.
CPC ...
Abstract

A method of fabricating a non-volatile memory device includes the steps of forming a lower conductive layer on a substrate, forming a lower and an upper sacrificial patterns on the substrate with the lower conductive layer, wherein the lower and upper sacrificial patterns include a trench exposing the lower conductive layer, forming mask spacers on sidewalls of the upper and lower sacrificial patterns, using the mask spacers and the upper sacrificial pattern as an etch mask, etching the exposed lower conductive layer to form a lower conductive pattern exposing the substrate, forming a plug conductive layer covering an entire surface of a substrate with the lower conductive pattern, and planarizingly etching the plug conductive layer until the lower sacrificial pattern is exposed, thereby forming a source plug in a gap region between the mask spacers that is connected to the substrate.


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