The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 17, 2005
Filed:
Mar. 07, 2003
James R. Hochschild, Plano, TX (US);
Donald C. Richardson, Plano, TX (US);
James R. Hochschild, Plano, TX (US);
Donald C. Richardson, Plano, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
The present invention accepts timing and clock signals with a desired frequency and undesired duty cycle CLKIN, and outputs a clock signal CLKOUT with the desired frequency and desired duty cycle. If the clock signal is known to have a duty cycle of greater than 50%, one exemplary embodiment of the present invention delays the rising edge of the clock signal so as to produce a clock signal with a 50% duty cycle. One exemplary embodiment of the present invention comprises a charge pump integrator () configured in a feedback loop, the output of the charge pump integrator () operable as a controlling node to delay inverter (). If the clock signal CLKIN at the input of the circuit has a duty cycle of greater than 50%, then the charge pump integrator () will, through PBIAS, cause delay inverterto delay of the rising edge of CLKIN through delay inverter (). The charge pump integrator, through PBIAS, drives the duty cycle of the clock signal towards 50%.