The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 17, 2005

Filed:

Jun. 20, 2003
Applicant:

Hidetaka Kodama, Tokyo, JP;

Inventor:

Hidetaka Kodama, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L007/00 ;
U.S. Cl.
CPC ...
Abstract

An integrated circuit comprising a circuit block whose power supply is controlled by waiting operation, is supplied which is able to prevent the occurrence of penetrating electricity caused by unstable signals output from the circuit block whose power supply was broken. In the integrated circuit, a mask signal is set at 'L' level before a power in the circuit block is broken, a latch circuit formed by a NAND and an inverter keeps a node in 'L' state, then when the power supply is broken and drops into “L” level, the output signal of the NAND is fixed in “H” level. Thus, from the circuit block, even if a unstable mask signal is output, the node keeps in “L” level, so that gate circuits become off.


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