The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 17, 2005
Filed:
Jul. 09, 2003
Yew-keong Chong, Duluth, GA (US);
David J. Klein, Duluth, GA (US);
Xinxin Shao, Duluth, GA (US);
Prashant Shamarao, Alpharetta, GA (US);
Brian K. Butka, Alpharetta, GA (US);
Yew-Keong Chong, Duluth, GA (US);
David J. Klein, Duluth, GA (US);
XinXin Shao, Duluth, GA (US);
Prashant Shamarao, Alpharetta, GA (US);
Brian K. Butka, Alpharetta, GA (US);
Integrated Device Technology, Inc., Santa Clara, CA (US);
Abstract
Impedance-matched output driver circuits include a first totem pole driver stage and a second totem pole driver stage. The first totem pole driver stage includes at least one PMOS pull-up transistor and at least one NMOS pull-down transistor therein that are responsive to a first pull-up signal and a first pull-down signal, respectively. The second totem pole driver stage has at least one NMOS pull-up transistor and at least one PMOS pull-down transistor therein that are responsive to a second pull-up signal and second pull-down signal, respectively. The linearity of the output driver circuit is enhanced by including a first resistive element that extends between the first and second totem pole driver stages. The first resistive element has a first terminal, which is electrically coupled to drain terminals of the at least one PMOS pull-up transistor and the at least one NMOS pull-down transistor in the first totem pole driver stage, and a second terminal, which is electrically coupled to source terminals of the at least one NMOS pull-up transistor and the at least one PMOS pull-down transistor in the second totem pole driver stage.