The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 17, 2005
Filed:
Jun. 25, 2002
Marino J. Martinez, Nashua, NH (US);
Ernest Schirmann, Lake Zurich, IL (US);
Olin L. Hartin, Phoenix, AZ (US);
Colby G. Rampley, Phoenix, AZ (US);
Mariam G. Sadaka, Phoenix, AZ (US);
Charles E. Weitzel, Mesa, AZ (US);
Julio Costa, Phoenix, AZ (US);
Marino J. Martinez, Nashua, NH (US);
Ernest Schirmann, Lake Zurich, IL (US);
Olin L. Hartin, Phoenix, AZ (US);
Colby G. Rampley, Phoenix, AZ (US);
Mariam G. Sadaka, Phoenix, AZ (US);
Charles E. Weitzel, Mesa, AZ (US);
Julio Costa, Phoenix, AZ (US);
Freescale Semiconductor, Inc., Schaumburg, IL (US);
Abstract
A method for fabricating an RF enhancement mode FET () having improved gate properties is provided. The method comprises the steps of providing () a substrate () having a stack of semiconductor layers () formed thereon, the stack including a cap layer () and a central layer () defining a device channel, forming () a photoresist pattern () over the cap layer, thereby defining a masked region and an unmasked region, and, in any order, (a) creating () an implant region () in the unmasked region, and (b) removing () the cap layer from the unmasked region. By forming the implant region and cap region with no overlap, a device with low current leakage may be achieved.