The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 17, 2005
Filed:
Aug. 15, 2002
Cheryl Anne Bollinger, Orlando, FL (US);
Seungmoo Choi, Allentown, PA (US);
William T. Cochran, Clermont, FL (US);
Stephen Arlon Meisner, Allen, TX (US);
Daniel Mark Wroge, Allentown, PA (US);
Gerard Zaneski, Macungie, PA (US);
Cheryl Anne Bollinger, Orlando, FL (US);
Seungmoo Choi, Allentown, PA (US);
William T. Cochran, Clermont, FL (US);
Stephen Arlon Meisner, Allen, TX (US);
Daniel Mark Wroge, Allentown, PA (US);
Gerard Zaneski, Macungie, PA (US);
Agere Systems, Inc., Allentown, PA (US);
Abstract
A method for manufacturing a semiconductor wafer uses a reticle having a plurality of spaced apart circuit images of identical patterns or images of a common level of a single integrated circuit formed on the reticle and arranged in columns and rows about its central point. At least one column of spaced apart test images are formed outside of and adjacent an outermost column of circuit images. Radiation is projected through the reticle for exposing the patterns on the reticle onto an underlying wafer. A reticle holder having a pair of shutter elements aligned parallel to the columns of images selectively blocks the projection of radiation through the columns of the test images but are exposed in order to form test circuits on the wafer at selected locations.