The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 17, 2005

Filed:

Oct. 09, 2002
Applicants:

Brenor Brophy, San Jose, CA (US);

Marc Hartranft, Scotts Valley, CA (US);

Syed Tariq Shafaat, Freeland, WA (US);

Jeff Hall, Atlanta, GA (US);

Inventors:

Brenor Brophy, San Jose, CA (US);

Marc Hartranft, Scotts Valley, CA (US);

Syed Tariq Shafaat, Freeland, WA (US);

Jeff Hall, Atlanta, GA (US);

Assignee:

Cypress Semiconductor Corp., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01R043/00 ;
U.S. Cl.
CPC ...
Abstract

A method of manufacturing a plurality of electro-optical sub-assemblies in parallel is provided. A plurality of printed circuit boards (PCBs) are preferably formed in a panel of flex material. Rigid substrates can be arranged along regions of the PCBs. A plurality of electrical components, including electro-optical semiconductor devices, are preferably located on the rigid substrates. Lens arrays are preferably aligned over the electro-optical semiconductor devices, such as through an alignment mechanism. The PCBs can then be singulated into individual electro-optical sub-assemblies. The rigid substrates can be a plurality of leadframes formed on a matrix leadframe. The matrix leadframe is preferably attached to the panel of flex material such that the leadframes are arranged in proximity to leadframe cutout regions of the PCBs. Electrical interconnections are then preferably formed between the electrical components on the leadframe and the PCBs.


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