The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 10, 2005
Filed:
Oct. 16, 2003
Hee-cheol Choi, Suwon, KR;
Hee-Cheol Choi, Suwon, KR;
Abstract
The present invention discloses a layout method of a comparator array of a flash type analog to digital converting circuit. The flash type analog to digital converting circuit includes a reference voltage for generating 2voltages and being arranged to be folded; a comparator array including (2−1) comparators for comparing voltage differences between the respective 2voltages and an analog input signal to generate a digital thermometer code having (2−1) bits and an encoder for encoding the digital thermometer code having (2−1) bits to generate an n-bit digital signal. The layout method of the flash type analog to digital converting circuit comprises arranging the comparators such that the comparators of (2−1)comparator to (2/2)comparator are arranged in order and the comparators of (2/2−1)comparator to a first comparator are arranged in reverse fashion between the comparators of the (2−1)comparator to the (2/2)comparator; and arranging the comparators such that the neighboring comparators adjacent to the respective (2−1) comparators remain at to the same state when the (2−1)comparator to the (2/2)comparator transit to different states respectively. Therefore, increasing of an offset voltage due to the effects of the neighboring comparators is prevented without increasing a layout area size.