The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 10, 2005

Filed:

Mar. 29, 2001
Applicants:

Yusuke Tsutsui, Hashima, JP;

Makoto Kitagawa, Gifu, JP;

Mitsugu Kobayashi, Nagoya, JP;

Hisao Uehara, Ogaki, JP;

Inventors:

Yusuke Tsutsui, Hashima, JP;

Makoto Kitagawa, Gifu, JP;

Mitsugu Kobayashi, Nagoya, JP;

Hisao Uehara, Ogaki, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G005/00 ;
U.S. Cl.
CPC ...
Abstract

A driving circuit of a display device such as a liquid crystal generates power supply clocks (and) based on a system clock during the normal display operation which is not a power save mode. The generated power supply clocks are supplied, directly or after inversion, to the switches (SWthrough SW(and SWthrough SW)) in a charge pump type power supply circuit () for switching the connection of capacitors (Cand C(and Cand C)) in the power supply circuit (). In this manner, supply voltages VDDand VDDwhich function as the driving power supply for a driving circuit () and a display panel () can be obtained at the power supply circuit () by boosting the input voltage Vin. The driving circuit () stops supply of the power supply clocks to the power supply circuit () when a transition to the power save mode is instructed and a power save control signal generated by a CPU I/F circuit () is changed, thereby suspending generation of the supply voltage an consumption of power consumption at the circuit and display panel.


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