The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 10, 2005
Filed:
Sep. 29, 1999
Erick M. Hirata, Torrance, CA (US);
Lloyd F. Linder, Agoura Hills, CA (US);
Erick M. Hirata, Torrance, CA (US);
Lloyd F. Linder, Agoura Hills, CA (US);
TelASIC Communications, Inc., El Segundo, CA (US);
Abstract
A crosspoint switch architecture (). The inventive architecture () includes a monolithic substrate () on which a plurality (N) of electrical inputs are provided. In addition, a plurality (M) of electrical outputs are provided on the substrate (). A switch is disposed on the substrate () for selectively interconnecting the inputs to the outputs and a control circuit () is disposed on the substrate () for controlling the switch. The switch comprises M, N to, multiplexers (), each multiplexer () being adapted to receive each of the N electrical inputs. In the illustrative embodiment, each of the N inputs to each of the multiplexers is received through a respective one of N switchable amplifiers (). The output of each amplifier () is provided to a respective one of N switchable isolation buffers (). The outputs of the buffers () are summed and buffered to provide the output of each multiplexer (). The control circuit () selects which input is to be passed through to the output of a given multiplexer (). In the illustrative embodiment, the control circuit () includes a serial in, parallel out shift register and decode logic circuitry.