The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 10, 2005

Filed:

Oct. 22, 2002
Applicants:

Harsh D. Sharma, Austin, TX (US);

Howard L. Levy, Cedar Park, TX (US);

Hong Kim, Austin, TX (US);

Nadeem N. Eleyan, Austin, TX (US);

Inventors:

Harsh D. Sharma, Austin, TX (US);

Howard L. Levy, Cedar Park, TX (US);

Hong Kim, Austin, TX (US);

Nadeem N. Eleyan, Austin, TX (US);

Assignee:

Sun Microsystems, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R023/02 ;
U.S. Cl.
CPC ...
Abstract

The locked frequency of a PLL is used to latch a test signal through various latching devices (flip-flops or the like). Various different delays are selectively applied to the test signal to provide a delayed test signal and the delayed test signal is measured to determine whether the delay in the test signal matches the jitter in the locked frequency of the PLL. When the delay in the test signal matches the jitter in the locked frequency of the PLL, the respective delay of the test-signal is used to determine the effective locked frequency of the PLL.


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