The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 10, 2005
Filed:
Feb. 24, 2003
Osamu Goto, Miyagi, JP;
Takeharu Asano, Miyagi, JP;
Motonobu Takeya, Miyagi, JP;
Katsunori Yanashima, Kanagawa, JP;
Shinro Ikeda, Miyagi, JP;
Katsuyoshi Shibuya, Miyagi, JP;
Yasuhiko Suzuki, Miyagi, JP;
Osamu Goto, Miyagi, JP;
Takeharu Asano, Miyagi, JP;
Motonobu Takeya, Miyagi, JP;
Katsunori Yanashima, Kanagawa, JP;
Shinro Ikeda, Miyagi, JP;
Katsuyoshi Shibuya, Miyagi, JP;
Yasuhiko Suzuki, Miyagi, JP;
Sony Corporation, Tokyo, JP;
Abstract
A nitride semiconductor having a large low-defect region in a surface thereof, and a semiconductor device using the same are provided. Also, a manufacturing method for a nitride semiconductor comprising a layer formation step using a transverse growth technique where surface defects can easily be reduced, and a manufacturing method for a semiconductor device using the same are provided. On a substrate, a seed crystal part is formed in a stripe pattern with a buffer layer in between. Next, crystals are grown from the seed crystal part in two stages of growth conditions to form a nitride semiconductor layer. Low temperature growing parts with a trapezoid shaped cross section are formed at a growth temperature of 1030° C. in the first stage and a transverse growth is dominantly advanced at a growth temperature of 1070° C. to form a high temperature growing part between the low temperature growing parts in the second stage. Thereby, hillocks and conventional lattice defects are reduced in a surface of the nitride semiconductor layer which is above the low temperature growing part.