The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2005

Filed:

Jan. 27, 2004
Applicants:

Cyrus Afghahi, Mission Viejo, CA (US);

Sami Issa, Phoenix, AZ (US);

Inventors:

Cyrus Afghahi, Mission Viejo, CA (US);

Sami Issa, Phoenix, AZ (US);

Assignee:

Broadcom Corporation, Irvine, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C007/00 ;
U.S. Cl.
CPC ...
Abstract

A system-on-chip (SOC) device or a random access memory (RAM) chip includes a RAM block. The RAM block includes memory cells, each of which has three transistors. Each memory cell is coupled to both a read bit line and a write bit line. A transparent continuous refresh mechanism has been implemented to read the content of a memory cell and re-write it back to the memory cell without disturbing the access (read/write) cycle, making refresh operations transparent to the system level. The continuous refresh mechanism includes a collision detection mechanism to prevent writing and reading the same memory cell at the same time.


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Afghahi, Cyrus. (2005). Memory device having simultaneous read/write and refresh operations with coincident phases (U.S. Patent No. 6888761). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6888761

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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