The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 03, 2005
Filed:
Oct. 11, 2001
Yasuhiko Takeo, Tokyo, JP;
Masatoshi Tobayashi, Tokyo, JP;
Masaki Hirose, Kanagawa, JP;
Yukio Akazawa, Kanagawa, JP;
Yasuhiko Takeo, Tokyo, JP;
Masatoshi Tobayashi, Tokyo, JP;
Masaki Hirose, Kanagawa, JP;
Yukio Akazawa, Kanagawa, JP;
NTT Electronics Corporation, Tokyo, JP;
Abstract
A phase detector circuit that prevents a significant loss of lock during input of CIDs (Consecutive Identical Digits) and has a high linearity of a phase to voltage conversion characteristic around a phase-locked point in an operation of comparing phases of random NRZ signals in a phase. By using the phase detector circuit having a circuit configuration containing a delay circuit and a combination of leapt a multiplier circuit and a subtractor circuit, a capability as the PLL circuit of preventing the significant loss of lock can be realized. In addition, since a duty cycle of a pulse appearing at an output terminalof a multiplier circuitapproaches 50% as a phase-locked state is approached, a distortion in the phase to voltage conversion characteristic does not appear, and thus high linearity of the phase to voltage conversion characteristic around thus phase-locked point can be realized.