The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 03, 2005
Filed:
Mar. 11, 2004
Harvey Newell Rogers, Playa Del Rey, CA (US);
Mark Kintis, Manhattan Beach, CA (US);
Harvey Newell Rogers, Playa Del Rey, CA (US);
Mark Kintis, Manhattan Beach, CA (US);
Northrop Grumman Corporation, Los Angeles, CA (US);
Abstract
An inexpensive package for a semiconductor chip () that incorporates a stress relief buffer () between a side of the chip and the metal carrier layer () to absorb thermally induced stress produced by significantly different rates of thermal expansion of the wafer and the metal carrier. The buffer () is formed by a polymer that is flexible and can be etched, contains a coefficient of thermal expansion that does not significantly differ from that of the chip and/or a combination of CET and elasticity that retains a physical connection with the side of the chip and the metal carrier over the temperature range of operation anticipated for the chip. Polyimide or paraylene are preferred examples. Vias () extend through the buffer to place the metal carrier electrically in common with the metal layer () found on the back surface of the wafer so that an electrical ground applied to the metal carrier layer () may extend through to that surface.