The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 03, 2005
Filed:
Jun. 10, 2003
Lawrence C. Gunn, Iii, Altadena, CA (US);
Giovanni Capellini, Los Angeles, CA (US);
Maxime Jean Rattier, Pasadena, CA (US);
Thierry J. Pinguet, Pasadena, CA (US);
Lawrence C. Gunn, III, Altadena, CA (US);
Giovanni Capellini, Los Angeles, CA (US);
Maxime Jean Rattier, Pasadena, CA (US);
Thierry J. Pinguet, Pasadena, CA (US);
Luxtera, Inc., Carlsbad, CA (US);
Abstract
Methods for deposition of a Ge layer during a CMOS process on a monolithic device are disclosed. The insertion of the Ge layer enables the conversion of light to electrical signals easily. As a result of this method, standard metals can be attached directly to the Ge in completing an electrical circuit. Vias can also be used to connect to the Ge layer. In a first aspect of the invention, a method comprises the step of incorporating the deposition of Ge at multiple temperatures in a standard CMOS process. In a second aspect of the invention, a method comprises the step of incorporating the deposition of poly-Ge growth in a standard CMOS process.