The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 03, 2005
Filed:
Nov. 24, 2003
Dae Woo Lee, Daejon-Shi, KR;
Tae Moon Roh, Daejon-Shi, KR;
Yil Suk Yang, Daejon-Shi, KR;
IL Yong Park, Pyeongtaek-Shi, KR;
Byoung Gon Yu, Daejon-Shi, KR;
Jong Dae Kim, Daejon-Shi, KR;
Dae Woo Lee, Daejon-Shi, KR;
Tae Moon Roh, Daejon-Shi, KR;
Yil Suk Yang, Daejon-Shi, KR;
Il Yong Park, Pyeongtaek-Shi, KR;
Byoung Gon Yu, Daejon-Shi, KR;
Jong Dae Kim, Daejon-Shi, KR;
Abstract
The present invention relates to structures of a high voltage device and a low voltage device formed on a SOI substrate and a method for manufacturing the same, and it is characterized in which the low voltage device region of silicon device regions in a SOI substrate is higher than the high voltage device region by steps, and a thickness of the silicon device region, where the high voltage device is formed, is equal to a junction depth of impurities of a source and drain in the low voltage device. Accordingly, silicon device regions in the SOI substrate are divided into the high voltage region and the low voltage region and steps are formed there between by oxidation growth method, so that the high voltage device having low junction capacitance can be made, and the low voltage device compatible with the conventional CMOS process and device characteristics can also be made at the same time.