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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6885803 B1

PDFFull Text
Expired
Date of Patent:
Apr. 26, 2005

Filed:

Jul. 14, 2003

Method to produce stress-free optical waveguides to reduce stress-induced birefringence in planar lightwave circuit (plc) devices

Applicants:

Devendra S. Chhabra, San Jose, CA (US);

Grace L. Gorman, San Jose, CA (US);

Inventors:

Devendra S. Chhabra, San Jose, CA (US);

Grace L. Gorman, San Jose, CA (US);

Assignee:

Headway Technologies, Inc., Milpitas, CA (US);

Attorneys:

George O. Saile

Stephen B. Ackerman

Stephen G. Stanton

Primary Examiner:

Brian Healy

Assistant Examiner:

Ryan Lepisto

Int. Cl.
CPC ...
G02B006/10 ;
U.S. Cl.
CPC ...
Abstract

A method of forming a waveguide comprising the following steps. A structure is provided. An underclad layer is formed over the structure and a core layer is formed over the underclad layer. Patterning: the core layer to form the waveguide; and partially into the underclad layer, forming an overetched underclad layer having a projection underneath the waveguide. The waveguide having stress gradients and the overetched underclad layer having stress gradients.

Find Patent Forward Citations

Chhabra, Devendra. (2005). Method to produce stress-free optical waveguides to reduce stress-induced birefringence in planar lightwave circuit (plc) devices (U.S. Patent No. 6885803). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6885803

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