The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 26, 2005

Filed:

Mar. 12, 2003
Applicants:

Michael F. Deering, Los Altos, CA (US);

Nathaniel David Naegle, Pleasanton, CA (US);

Ranjit S. Oberoi, Saratoga, CA (US);

Inventors:

Michael F. Deering, Los Altos, CA (US);

Nathaniel David Naegle, Pleasanton, CA (US);

Ranjit S. Oberoi, Saratoga, CA (US);

Assignee:

Sun Microsystems, Inc., Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G09G005/00 ; G06F012/02 ;
U.S. Cl.
CPC ...
Abstract

A system and method are disclosed for reproducing a pre-selected larger 2-D sample location pattern from a smaller one by means of X,Y address permutation. This method, for example, allows hardware to effectively reproduce a pre-selected set of sample locations for an array of 128×128 sample bins from a smaller set of pre-selected sample locations for an array of 2×2 sample bins. A permutation logic unit may use a first portion of an address for a sample bin B to identify a corresponding 2-D transformation, apply the inverse of the transformation to a second portion of the sample bin address to identify the corresponding bin of the 2×2 array of sample bins, and apply the transformation to the sample locations stored in the corresponding bin to reproduce the sample locations pre-selected for sample bin B.


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