Signal generation using dac having selectively switched registers storing output values

Abstract

A signal generator () for generating a square waveform analog voltage output signal comprises an on-chip DAC () which outputs the analog voltage signal on an output terminal (). On-chip first and second programmable registers () store first and second digital words which correspond to the maximum and minimum voltage values of the analog output signal. An on-chip switch circuit () selectively and alternately switches the first and second registers () to an on-chip DAC register () from which the respective first and second digital words are loaded into the DAC () in response to a load DAC signal generated by a control circuit (). The load DAC signal is generated in response to an externally generated LDAC signal in the form of a clock signal which is applied to an LDAC terminal (). A flip-flop () in response to the load DAC signal outputs a control signal on a control line () for alternately switching the first and second registers () to the DAC register (). The frequency of the analog output signal is determined by the frequency of the LDAC signal, and is half the frequency of the LDAC signal.