Low-power phase-locked-loop and method using quadrature phase-signals at one-half the output frequency

Abstract

A phase-locked loop includes a voltage-controlled oscillator (VCO) to generate a plurality of quadrature-phase signals at one-half an output frequency in response to bias signals. The VCO also includes a times-two multiplier biased by the bias signals to generate the output frequency from the quadrature-phase signals. The bias signals include a load-element bias signal to concurrently bias load elements of buffer stages of the VCO and substantially identical load elements of the multiplier. The bias signal also include a current-source bias signal to concurrently bias current sources of the buffer stages of the VCO and a substantially identical buffer stage of the multiplier. The VCO operating at one-half the output frequency together with the multiplier may consume less power than the VCO when operating at the output frequency.