The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6885096 B1

PDF
Full Text
Expired
Date of Patent:
Apr. 26, 2005

Filed:

Jul. 10, 2001
Applicants:

Fumio Hirahara, Yokohama, JP;

Kenichi Ogata, Yokohama, JP;

Inventors:

Fumio Hirahara, Yokohama, JP;

Kenichi Ogata, Yokohama, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L023/48 ; H01L023/495 ; H01L023/34 ;
U.S. Cl.
CPC ...
Abstract

The present has an object of reducing a wiring resistance caused by the wiring metal such as bonding wire, and self-inductance, in a semiconductor device for large power, such as IGBT module. Therefore, the invention has at lest three or more power terminals superimposed on each other, wherein at least one semiconductor chip is connected electrically in a way to be sandwiched between predetermined two power terminals among the power terminals. A power terminal on one end among the aforementioned superposed power terminals and a power terminal on the other end among the superposed power terminals can be led out in the same direction, for example.


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