The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 26, 2005
Filed:
Feb. 14, 2003
Saburo Tagami, Matsumoto, JP;
Takashi Kobayashi, Matsumoto, JP;
Fumiaki Kirihata, Matsumoto, JP;
Satoshi Kuboyama, Tokyo, JP;
Saburo Tagami, Matsumoto, JP;
Takashi Kobayashi, Matsumoto, JP;
Fumiaki Kirihata, Matsumoto, JP;
Satoshi Kuboyama, Tokyo, JP;
Fuji Electric Co., Ltd., Kanagawa, JP;
National Space Development Agency of Japan, Ibaraki, JP;
Abstract
In a power MOSFET, on an Ndrain layeras a substrate, a second N base layerand a first Nbase layerare deposited in the order by epitaxial growth. In a surface portion of the layer, there are selectively formed a P base region, in a surface portion of which an Nsource regionis selectively formed. On a channel region in the P base region, a gate electrodeis formed with a gate insulator filmheld between. A source electrodeand a drain electrodeare formed on the Nsource regionand on the back of the substrate, respectively. The layeris made to have a thickness equal to or more than ¼ of that of the first Nbase layer, and an averaged impurity concentration between 1×10/cmand 3×10/cm. The thickness can be alternatively given as equal to or more than ½ of a difference between the thickness x shown as x(μm)=V(V)/8 and that of the layer, where Vis an SEB(Single Event Burnout) voltage of the layer. This makes positive feed back hard to occur between latch-up of a parasitic npn transistor and dynamic avalanche near the substrate to enhance the SEB voltage, allowing the MOSFET to be applied to space use.