The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 26, 2005

Filed:

Jul. 16, 2003
Applicants:

Hwa Sung Rhee, Seoul, KR;

Nae IN Lee, Seoul, KR;

Jung IL Lee, Yong-In, KR;

Sang Su Kim, Yong-In, KR;

Bae Geum Jong, Suwon, KR;

Inventors:

Hwa Sung Rhee, Seoul, KR;

Nae In Lee, Seoul, KR;

Jung Il Lee, Yong-In, KR;

Sang Su Kim, Yong-In, KR;

Bae Geum Jong, Suwon, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L021/3205 ; H01L021/336 ; H01L021/4763 ;
U.S. Cl.
CPC ...
Abstract

A semiconductor device includes a hetero grain stack gate (HGSG). The device includes a semiconductor substrate having a surface, a gate insulating layer formed over the surface of the semiconductor substrate, and a gate electrode formed over the gate insulating layer, wherein the gate electrode includes a lower poly-SiGe layer having a columnar crystalline structure, and an upper poly-Si layer having a random crystalline structure. In one embodiment, the gate electrode includes a lower poly-SiGe layer having a columnar crystalline structure, an intermediate layer having an random crystalline structure, and an upper poly-Si layer having a columnar crystalline structure. A method of manufacturing a semiconductor device having an HGSG comprises depositing a gate insulating layer over a surface of a semiconductor substrate, depositing a lower poly-SiGe layer having a columnar crystalline structure over the gate insulating layer, depositing an amorphous Si layer over the lower poly-SiGe layer, and crystallizing the amorphous Si layer to obtain an upper poly-Si layer having a random crystalline structure.


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